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cy7c1018dv33 cy7c1019dv33 1-mbit (128 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05481 rev. *i revised november 19, 2014 1-mbit (128 k 8) static ram features pin- and function-compatible with cy7c1018cv33 and cy7c1019cv33 high speed ? t aa = 10 ns low active power ? i cc = 60 ma @ 10 ns low cmos standby power ? i sb2 = 3 ma 2.0 v data retention automatic power-down when deselected cmos for optimum speed/power center power/ground pinout easy memory expansion with ce and oe options available in pb-free 32-pin 400-mil wide molded soj, 32-pin tsop ii and 48-ball vfbga packages functional description the cy7c1018dv33/cy7c1019dv33 is a high-performance cmos static ram organized as 131,072 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and three-state drivers. this device has an aut omatic power-down feature that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pi ns will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low). the cy7c1018dv33/cy7c1019dv33 are available in pb-free 32-pin 400-mil wide molded soj, 32-pin tsop ii and 48-ball vfbga packages. for a complete list of related documentation, click here . a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps inputbuffer power down we oe i/o 0 ce i/o 1 i/o 2 i/o 3 i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 13 a 11 a 12 a 9 a 10 128k 8 array a 14 a 15 a 16 logic block diagram
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 2 of 19 contents selection guide ................................................................ 3 pin configurations ........................................................... 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 17 document conventions ................................................. 17 units of measure ....................................................... 17 document history page ................................................. 18 sales, solutions, and legal information ...................... 19 worldwide sales and design s upport ......... .............. 19 products .................................................................... 19 psoc? solutions ...................................................... 19 cypress developer community ................................. 19 technical support ................. .................................... 19
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 3 of 19 selection guide description -10 (industrial) unit maximum access time 10 ns maximum operating current 60 ma maximum standby current 3ma pin configurations figure 1. 48-ball vfbga pinout (top view) [1] figure 2. 32-pin soj / tsop ii pinout (top view) we v cc a 9 a 16 nc a 4 a 2 a 1 ce nc i/o 0 i/o 1 a 5 a 0 nc nc nc i/o 2 i/o 3 v ss a 10 a 3 oe v ss nc i/o 7 nc nc a 13 a 7 a 6 nc v cc i/o 6 nc nc nc i/o 4 i/o 5 a 8 a 11 a 14 a 12 a 15 nc nc nc 3 2 6 5 4 1 d e b a c f g h nc top view soj/tsopi 1 2 3 4 5 6 7 8 9 10 11 14 19 20 24 23 22 21 25 28 27 26 12 13 29 32 31 30 16 15 17 18 a 7 a 1 a 2 a 3 ce i/o 0 i/o 1 v cc i/o 2 a 0 a 4 a 5 a 6 i/o 3 we v ss we v cc a 9 a 16 nc a 4 a 2 a 1 ce a 5 a 0 a 3 v ss nc i/o 7 nc a 13 a 7 a 6 i/o 6 nc nc nc i/o 4 i/o 5 a 8 a 11 a 14 a 12 a 15 nc d e b a c f g h nc 1 2 3 4 5 6 7 8 9 10 11 14 19 20 24 23 22 21 25 28 27 26 12 13 29 32 31 30 16 15 17 18 a 7 a 1 a 2 a 3 ce i/o 0 i/o 1 v cc a 13 a 16 a 15 oe i/o 7 i/o 6 a 12 a 11 a 10 a 9 i/o 2 a 0 a 4 a 5 a 6 i/o 4 v cc i/o 5 a 8 i/o 3 we v ss a 14 v ss note 1. nc pins are not connected on the die.
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 4 of 19 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied ... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc to relative gnd [2] ...............................?0.3 v to +4.6 v dc voltage applied to outputs in high z state [2] ................................ ?0.3 v to v cc + 0.3 v dc input voltage [2] ............................ ?0.3 v to v cc + 0.3 v current into outputs (low) .... .................................... 20 ma static discharge voltage (per mil-std-883, method 3015) .............. ............ > 2001 v latch-up current .................................................... > 200 ma operating range range ambient temperature v cc speed industrial ?40 ? c to +85 ? c3.3 v ? 0.3 v 10 ns electrical characteristics over the operating range parameter description test conditions -10 (industrial) unit min max v oh output high voltage min v cc , i oh = ?4.0 ma 2.4 ? v v ol output low voltage min v cc , i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 v i ix input leakage current gnd < v in < v cc ?1 +1 ? a i oz output leakage current gnd < v in < v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc 100 mhz ? 60 ma 83 mhz ? 55 ma 66 mhz ? 45 ma 40 mhz ? 30 ma i sb1 automatic ce power-down current ? ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max ?10ma i sb2 automatic ce power-down current ? cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v, f = 0 ?3ma note 2. v il(min) = ?2.0 v and v ih(max) = v cc + 1 v for pulse durations of less than 5 ns.
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 5 of 19 capacitance parameter [3] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3 v 8 pf c out output capacitance 8pf thermal resistance parameter [3] description test conditions 32-pin soj 32-pin tsop ii 48-ball vfbga unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 56.29 62.22 36 ? c/w ? jc thermal resistance (junction to case) 38.14 21.43 9 ? c/w ac test loads and waveforms figure 3. ac test loads and waveforms [4] 90% 10% 3.0 v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 ? 50 ? 1.5v (b) (a) 3.3 v output 5 pf (c) r1 317 ? r2 351 ?? high-z characteristics: notes 3. tested initially and after any design or proces s changes that may affect these parameters. 4. ac characteristics (except high z) are te sted using the load conditions shown in figure 3 (a). high z characteristics are tested for all speeds using the test load shown in figure 3 (c).
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 6 of 19 data retention characteristics over the operating range parameter description conditions min max unit v dr v cc for data retention 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v ?3ma t cdr [5] chip deselect to data retention time 0?ns t r [6] operation recovery time t rc ?ns data retention waveform figure 4. data retention waveform 3.0 v 3.0 v t cdr v dr > 2 v data retention mode t r ce v cc notes 5. tested initially and after any design or process changes that may affect these parameters. 6. full device operation requires linear v cc ramp from v dr to v cc(min.) > 50 ? s or stable at v cc(min.) > 50 ? s.
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 7 of 19 switching characteristics over the operating range parameter [7] description -10 (industrial) unit min max read cycle t power [8] v cc (typical) to the first access 100 ? ? s t rc read cycle time 10 ? ns t aa address to data valid ? 10 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 10 ns t doe oe low to data valid ? 5 ns t lzoe oe low to low z [9] 0? ns t hzoe oe high to high z [9, 10] ?5 ns t lzce ce low to low z [9] 3? ns t hzce ce high to high z [9, 10] ?5 ns t pu [11] ce low to power-up 0 ? ns t pd [11] ce high to power-down ? 10 ns write cycle [12, 13] t wc write cycle time 10 ? ns t sce ce low to write end 8 ? ns t aw address set-up to write end 8 ? ns t ha address hold from write end 0 ? ns t sa address set-up to write start 0 ? ns t pwe we pulse width 7? ns t sd data set-up to write end 5 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [9] 3? ns t hzwe we low to high z [9, 10] ?5 ns notes 7. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v. 8. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access can be performed. 9. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 10. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in figure 3 on page 5 (c). transition is measured when the outputs enter a high impedance state. 11. this parameter is guaranteed by design and is not tested. 12. the internal write time of the memory is defined by the overlap of ce low and we low. ce and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that term inates the write. 13. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd .
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 8 of 19 switching waveforms figure 5. read cycle no. 1 (address transition controlled) [14, 15] figure 6. read cycle no. 2 (oe controlled) [15, 16] previous data valid data out valid rc t aa t oha t rc address data i/o 50% 50% data out valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high icc isb impedance oe ce address data i/o v cc supply current notes 14. device is continuously selected. oe , ce = v il . 15. we is high for read cycle. 16. address valid prior to or coincident with ce transition low.
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 9 of 19 figure 7. write cycle no. 1 (ce controlled) [17, 18] figure 8. write cycle no. 2 (we controlled, oe high during write) [17, 18] switching waveforms (continued) t wc data in valid t aw t sa t pwe t ha t hd t sd t sce t sce ce we data i/o address t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid note 19 ce address we data i/o oe notes 17. data i/o is high impedance if oe = v ih . 18. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 19. during this period the i/os are in the output state and input signals should not be applied.
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 10 of 19 figure 9. write cycle no. 3 (we controlled, oe low) [20, 21] switching waveforms (continued) data in valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe note 22 ce address we data i/o notes 20. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 21. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 22. during this period the i/os are in the output state and input signals should not be applied.
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 11 of 19 truth table ce oe we i/o 0 ?i/o 7 mode power h x x high z power-down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high z selected, outputs disabled active (i cc )
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 12 of 19 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 10 cy7c1018dv33-10vxi 51-85041 32-pin (300-mil) molded soj (pb-free) industrial cy7c1019dv33-10vxi 51-85033 32-pin (400-mil) molded soj (pb-free) cy7c1019dv33-10zsxi 51-85095 32-pin tsop type ii (pb-free) CY7C1019DV33-10BVXI 51-85150 48-ball vfbga (pb-free) please contact your local cypress sales r epresentative for availability of these parts. temperature range: i = industrial pb-free package type: xx = v or zs or bv v = 32-pin molded soj zs = 32-pin tsop type ii bv = 48-ball vfbga speed: 10 ns voltage range: v33 = 3 v to 3.6 v process technology: d = c9, 90 nm data width: x = 8 or 9 8/9 = 8-bits density: 01 = 1-mbit density family code: 1 = fast asynchronous sram family technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c cy 1 - 10 xx 7 01 v33 i d x x
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 13 of 19 package diagrams figure 10. 32-pin soj (400 mils) v32.4 (mo lded soj v33) package outline, 51-85033 51-85033 *e
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 14 of 19 figure 11. 32-pin soj (300 mils) v32.3 (catalog 32.3 molded soj) package outline, 51-85041 package diagrams (continued) 51-85041 rev. *d
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 15 of 19 figure 12. 32-pin tsop ii (20.95 11 .76 1.0 mm) zs32 package outline, 51-85095 package diagrams (continued) 51-85095 *b
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 16 of 19 figure 13. 48-ball vfbga (6 8 1.0 mm) bv48/bz48 package outline, 51-85150 package diagrams (continued) 51-85150 *h
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 17 of 19 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable soj small outline j-lead sram static random access memory tsop thin small outline package ttl transistor-transistor logic vfbga very fine-pitch ball grid array we write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ? s microsecond ma milliampere mm millimeter ns nanosecond ? ohm % percent pf picofarad v volt w watt
cy7c1018dv33 cy7c1019dv33 document number: 38-05481 rev. *i page 18 of 19 document history page document title: cy7c1018dv33/cy7c1019dv33, 1-mbit (128 k 8) static ram document number: 38-05481 rev. ecn no. issue date orig. of change description of change ** 201560 see ecn swi advance information data sheet for c9 ipp *a 233750 see ecn rkf dc parameters modified as per eros (spec # 01-02165 rev *a) pb-free offering in ordering information *b 262950 see ecn rkf added data retention characteristics table added t power spec in switching characteristics table shaded ordering information *c 307598 see ecn rkf reduced speed bins to -8 and -10 ns *d 520652 see ecn vkn changed status from preliminary to final removed commercial operating range removed 8 ns speed bin added i cc values for the frequencies 83 mhz, 66 mhz and 40 mhz added 48-ball vfbga package updated thermal resistance table updated ordering information table changed overshoot spec from v cc + 2 v to v cc + 1 v in footnote #3 *e 3110052 12/14/2010 aju added ordering code definitions . updated package diagrams . *f 3416342 10/20/2011 tava updated functional description (removed the note ?for guidelines on sram system design, please refer to the ?system design guidelines? cypress application note, available on the internet at www.cypress.com .? and its reference in functional description ). updated electrical characteristics . updated switching waveforms . updated package diagrams . added acronyms and units of measure . updated in new template. *g 4324792 03/28/2014 vini added cy7c1018dv33 related information across the document. updated ordering information (updated part numbers). updated package diagrams : spec 51-85033 ? changed revision from *d to *e. spec 51-85150 ? changed revision from *g to *h. updated in new template. *h 4531367 10/10/2014 nile corrected the package diagram reference for cy7c1018dv33 in (updated part numbers). added 51-85041: 32-pin (300 mil) molded soj in package diagrams : *i 4574311 11/19/2014 nile added related documentation hyperlink in page 1. updated figure 11 in package diagrams (spec 51-85041 rev. *c to *d).
document number: 38-05481 rev. *i revised november 19, 2014 page 19 of 19 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1018dv33 cy7c1019dv33 ? cypress semiconductor corporation, 2004-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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